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   REPLY: <9Nn*Sa1Cz@news.chiark.greenend.org.uk> dcd970e7   
   PID: SoupGate-Win32 v1.05   
   On 14/02/2024 22:37, Theo wrote:   
   > That's about right - ARM1/ARM2 was designed specifically for the Archimedes,   
   > and various design decisions that remain in Aarch32 are because of specific   
   > constraints on that platform.  For example ARM2 had no cache and was   
   > designed to make best use of FPM DRAM.  Every instruction took two cycles   
   > except some where sequential memory accesses could be completed in a single   
   > cycle - hence LDM/STM instructions.   
      
   I know what you mean there, but just to clarify, the majority of   
   arithmetic instructions took one cycle (except an extra cycle when using   
   shift by a register or where the PC was the destination, and multiplies   
   were up to 3 cycles).   
      
   Memory loads and stores were two cycles, one to set up the transfer and   
   one to do the transfer, but the memory system allowed a read or write to   
   the next word in just one cycle. So the LDM and STM instructions were   
   included which could transfer from 1 to 16 registers at a cost of 1 +   
   number of registers transferred cycles (as long as it was within the   
   same memory page). That did make quite a high upper bound on the   
   interrupt latency though, which was an issue for real-time use.   
      
   Strange how I can remember that from 35 years ago, but then you only had   
   to know a few classes of instruction timings in order to be able to   
   write highly optimised assembler. It became more and more complex with   
   each subsequent ARM generation, and has been best left to a compiler for   
   quite a while.   
      
   ---druck   
      
   --- SoupGate-Win32 v1.05   
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