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   XPost: sci.electronics.design   
      
   On 16 Jan 2024 15:57:32 GMT, Michael Schwingen   
    wrote:   
      
   >On 2024-01-16, John Larkin  wrote:   
   >>>If you want something nice with level translation that handles power   
   >>>sequencing between Pi and Target board, the JTAG Hat should do what you   
   >>>want:   
   >>>   
   >>>https://github.com/mschwingen/hardware/tree/master/JTAG_hat   
   >>>   
   >>>I think this should also work an a pi400.   
   >>   
   >> Is there a schematic somewhere?   
   >   
   >It is linked in the description:   
   >   
   >https://github.com/mschwingen/hardware/tree/master/JTAG_hat/pcb_ms_v3/Doc   
   >   
   >It's basically a bunch of 74LVC2T45 (which handle the "one side powered   
   >down" as well as the level-shifting), plus open-drain drivers for the reset   
   >signals. Note that you need to switch direction for the SWDIO signal, the   
   >rest is unidirectional.   
   >   
   >cu   
   >Michael   
      
   Do you think it's worth buffering the SW Debug pins? I was thinking I   
   might buffer the clock, since it's unidirectional and maybe   
   edge/impedance sensitive. I have no idea what the timing from the   
   Pi400 will be like, but people seem to use breadboards and dangling   
   wires and get away with it.   
      
   If the rate is reasonably low, the SWDIO data line won't matter much.   
      
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