Thunderbird/5.0   
   .pc.hardware.chips,comp.os.os2.misc   
   UTC)   
   .os2.setup.misc:592 comp.sys.ibm.pc.hardware.chips:1328 comp.os.os2.misc:3569   
   From: Jonathan de Boyne Pollard    
      
   > I found this interesting IOAPIC note   
   > (http://www.o3one.org/tutorials/apicarticle.txt), it explains the   
   functionality   
   > in accessible terms.   
      
   It gets three things quite wrong, however:   
      
   * There is a means of querying the firmware for the mainboard's PCI    
   interrupt wiring matrix.  It's the "$PIR" table.   
      
   * Many more than just "usually only [...] multiprocessor boards" have    
   I/O APICs.  This is because an I/O APIC is built in to several    
   southbridges.  A VIA VT8235M(CD) has a built-in I/O APIC, for example.    
   The mainboard manufacturer may well not have wired it up to the APIC    
   bus, but it's there.   
      
   * The swapping of INTIN #0 and INTIN #2 on the I/O APIC relative to IRQ    
   #0 and IRQ #2 at the dual 8259s isn't universal.  It happens for some    
   southbridges that have built-in I/O APICs.  But for southbridges that    
   use external I/O APIC chips the wiring is up to the mainboard    
   manufacturer, who can choose whatever wiring xe likes.  How the I/O APIC    
   is wired up is something that has to be read out of the MPS or ACPI    
   tables, constructed by the mainboard manufacturer and supplied in    
   firmware.  (I'm sure that M. Rieker discovered this when running xyr    
   program under Bochs.  Bochs emulates one of the chipsets that requires    
   an external I/O APIC chip.  It emulates such a chip being present, but    
   wires it up *without* swapping INTIN #0 and INTIN #2: a fact that system    
   software has to read the Bochs firmware-supplied MPS table to discover.)   
      
   --- Internet Rex 2.31   
    * Origin: virginmedia.com (1:261/20.999)