Anssi Saari  wrote:   
   > frank  writes:   
   >   
   > I also enjoyed your videos, nice work.   
      
   thank you!   
   >   
   >   
   > Did you get volunteers to help with the 8701? From a quick look the 8701   
      
   nobody so far, but I am almost at the prototype level by now   
      
   >   
   > just divides its input clock by 7 or 9 which is easy enough to implement   
      
   not so... It has an internal xtal oscillator, probably just a NOT gate,   
   then probably first multiply the xtal frequency by two, then it divides by 9   
   or 7. The net result is that it produces two outputs:   
   1) the xtal frequency (which is 4 x color carrier of PAL or NTSC video)   
   2) xtal * 4/9 for PAL or xtal * 4/7  for NTSC   
   3) the two outputs must be "phase locked" and they have 50% duty cycle   
      (I'm not sure the 50% duty cycle is needed, but I'm quite sure the phase   
       lock is needed).   
      
   As far as I know, it obtains the phase lock by means of digital delays, it   
   doesn't actually implement a true PLL internally.   
   On the other hand, older revisions of the C=64 boards (up until 251138 afair)   
   use a true PLL composed by 4 chips + the VIC-II internal divide by 8.   
      
   > on any programmable device although I don't know if the quality is good   
   > enough. OTOH, small FPGAs with a or two PLL included are cheaps these   
   > days.   
      
   well, currently I ruled out the FPGA solution since 5V parts are almost   
   extinct and since many of them can't be soldered with my equipment and skills.   
   I do SMD works (for example a small RAM module expansion for Tandy TRS-80 M100   
   and clones), but I won't bother with bga and similar packages :-)   
      
   I changed my mind again, implementing a fixed delays solution like MOS   
   engineers did, would be too tedious (imho) and anyway, the smallest CPLD   
   that doesn't require a custom programmer is probably the ATF1502 now, and   
   that's a 44 pin chip, a bit overkill maybe. I'll try to implement a 6522 or   
   6526 with it instead :-)   
      
   I'm breadboarding a PLL currently composed by 4 HC logic chips and passives.   
   If it works, the SMD version won't be too large, considering that one   
   of the HC chips will be substituted by 2 x sot-23 single gates and   
   the other 3 will be soic-16.   
   It can live on a small daughterboard that plugs into the original 8701   
   socket. The C=64 board has no space problems for one of them, I need   
   to check the space on the C=64C board anyway.   
   I'm not an expert on designing PLL loop filters and VCOs, but probably   
   a bit of component tuning will get me on track (I hope) :-)   
   I can't blindly copy the original PLL design since it uses the divide-by-8   
   inside the VIC-II and that signal isn't present on the 8701 socket as   
   far as I know, so I had to re-design a PLL with a separate divide-by-8   
   solution and if I would use the original design, that would make the chip   
   count go at least to 5, not counting that the MC4044 isn't easily found   
   nowadays.   
   So, new PLL with different chips (available at mouser, digikey, anywhere).   
   Any PLL guru here? :-)   
      
   Regards   
   Frank  IZ8DW   
      
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