Ref: 10630007
Title: GS/X.25 Clocking Configuration Mask Error on SIO-v.35s
Date: 8/30/90

Copyright 3Com Corporation, 1991.  All rights reserved.

This topic explains an error in the printed circuit board mask
on the SIO-V.35S board that is found in the GS/X.25-XNS and/or
the GS/X.25-IP.  The error affects the SIO clock configuration.

The SIO board areas E49, E69, and E70 determine whether the clock sources
are internal or external.  The mask for the area E70 is reversed in the
specification of "E" for external and "I" for internal clocking.  When
setting these jumpers, use the following table and refer to the actual
shorting plug numbers.  Here are the shorting plug settings for the
SIO-V.35S clock sources:

Port    Clock          Line    E49 Pins    E69 Pins    E70 Pins
No.     Source         Name    Connected   Connected   Connected
----    ------         ----    ---------   ---------   ---------
0       TX External    SCT        1-2*        2-3*        2-3*
0       TX Internal    SCTE       2-3         1-2         1-2
0       RX External    SCR        4-5*        n/a         n/a
0       RX Internal    --         5-6         n/a         n/a

1       TX External    SCT        7-8*        5-6*        5-6*
1       TX Internal    SCTE       8-9         4-5         4-5
1       RX External    SCR       10-11*       n/a         n/a
1       RX Internal    --        11-12        n/a         n/a

            *   Factory default, user-alterable.

The recommended settings vary according to the type of device being
attached.  In general, for use with modem equipment, both transmit and
receive clock sources should be set to external.  For direct connection,
in general, the transmit clock should be set to internal and the receive
clock to external.
