Pin Assignments and Cable Information All Interfaces

===================================================================
ST412 Interface (MFM and RLL) ST-506 was predecessor without buffered
seek
2 Cables: 1 each 34-pin Command Cable and 1 each 20-pin Data Cable
-------------------------------------------------------------------

J1 (34-pin Command) Host/Drive Pin Assignments

     GROUND RTN     SIGNAL PIN     SIGNAL
        PIN
_____________________________________________________

                                                 3
         1              2          -HEAD SELECT 2
                                                 2
         3              4          -HEAD SELECT 2

         5              6          -WRITE GATE

         7              8*         -SEEK COMPLETE

         9             10*         -TRACK 0

        11             12*         -WRITE FAULT
                                                 0
        13             14          -HEAD SELECT 2

        15             16          -RESERVED
                                                 1
        17             18          -HEAD SELECT 2

        19             20*         -INDEX

        21             22*         -READY

        23             24          -STEP

        25 (29)**      26 (28)     -DRIVE SELECT 1 (2)

        27 (27)        28 (26)     -DRIVE SELECT 2 (1)

        29 (25)        30          -DRIVE SELECT 3

        31             32          -DRIVE SELECT 4

        33             34          -DIRECTION IN

     * STATUS ENABLED WITH DRIVE SELECT
    ** TWISTED CABLE IN PARENTHESES


J2 (20-pin Data) HOST/DRIVE PIN ASSIGNMENTS


     GROUND RTN     SIGNAL PIN     SIGNAL NAME
        PIN
_____________________________________________________________


         2              1          -DRIVE SELECTED

         4              3          RESERVED

         6              5          RESERVED

         8              7          RESERVED

        10              9          RESERVED

        12             11          GROUND

                       13          +MFM (RLL) WRITE DATA

                       14          -MFM (RLL) WRITE DATA

        16             15          GROUND

                       17          +MFM (RLL) READ DATA

                       18          -MFM (RLL) READ DATA

        20             19          GROUND



==================================================================
ESDI (Enhanced Small Device Interface)
2 Cables: 1 each 34-pin Command Cable and 1 each 20-pin Data Cable
------------------------------------------------------------------


               ESDI INTERFACE SPECIFICATIONS


            ESDI CONTROL CABLE (J1/P1 PIN ASSIGNMENTS
             (Disk Implementation - Serial Mode)


                                    SIGNAL         GROUND
   SIGNAL NAME                       PIN             PIN
________________________________________________________________________

   -HEAD SELECT 2(3)                   2              1

   -HEAD SELECT 2(2)                   4              3

   -WRITE GATE                         6              5

   -CONFIGURATION/STATUS DATA          8              7

   -TRANSFER ACK                      10              9

   -ATTENTION                         12             11

   -HEAD SELECT 2(0)                  14             13

   -SECTOR/BYTE CLOCK/
    ADDRESS MARK FOUND                16             15

   -HEAD SELECT 2(1)                  18             17

   -INDEX                             20             19

   -READY                             22             21

   -TRANSFER REQ                      24             23

   -DRIVE SELECT 2(0)                 26             25

   -DRIVE SELECT 2(1)                 28             27

   -DRIVE SELECT 2(2)                 30             29

   -READ GATE                         32             31

   -COMMAND DATA                      34             33



             ESDI DATA CABLE (J2/P2) PIN ASSIGNMENTS
             (Disk Implementation - Serial Mode)


                                    SIGNAL         GROUND
   SIGNAL NAME                        PIN            PIN
________________________________________________________________________

   -DRIVE SELECTED                     1

   -SECTOR/BYTE CLOCK/
    ADDRESS MARK FOUND                 2

   -COMMAND COMPLETE                   3

   -ADDRESS MARK ENABLE                4

   GROUND                                             5

   +/-WRITE CLOCK                     7/8             6

   +/-READ REF CLOCK                 10/11           9/12

   +/-NRZ WRITE DATA                 13/14          15/16

   +/-NRZ READ DATA                  17/18            19

   -INDEX                              20




==================================================================
SCSI-1 (SMALL COMPUTER SYSTEM INTERFACE) CONNECTOR PIN ASSIGNMENTS
50-pin Cable
------------------------------------------------------------------

SCSI - Standard

SCSI (Small Computer System Interface) is an intelligent device
interface that allows up to 8 devices (usually 7 plus the host system)
to be connected together using up to a 6 meter cable. Unlike other
older interfaces, requests on a SCSI bus are just that, requests. For
example, rather than the low-level device commands like the familiar
STEP+ and STEP- of ST412, SCSI accesses data using the higher level
SEEK to a location ( LBA or logical block address on drives ).

Input voltages may vary from a low of 0VDC to a high of +5.25VDC.
These devices ARE NOT BUS COMPATIBLE with differential SCSI devices.
They are hovever command compatible. Attempting to share the SCSI bus
with a differential device will quite possibly damage the single-ended
SCSI device. Pin designations are as follows, and all signals are
active low (true is a voltage level between 0 and +0.8 VDC, and false
is defined as a voltage between +2 and +5.25 VDC).

Ŀ
PIN NUMBERSIGNAL DESCRIPTION PIN NUMBERSIGNAL   DESCRIPTION   
Ĵ
    1      GND   GROUND          26    TERMPWR TERMINATION PWR
Ĵ
    2      DB0   DATA BIT 0      27      GND    GROUND        
Ĵ
    3      GND   GROUND          28      GND    GROUND        
Ĵ
    4      DB1   DATA BIT 1      29      GND    GROUND        
Ĵ
    5      GND   GROUND          30      GND    GROUND        
Ĵ
    6      DB2   DATA BIT 2      31      GND    GROUND        
Ĵ
    7      GND   GROUND          32      ATN    ATTENTION     
Ĵ
    8      DB3   DATA BIT 3      33      GND    GROUND        
Ĵ
    9      GND   GROUND          34      GND    GROUND        
Ĵ
   10      DB4   DATA BIT 4      35      GND    GROUND        
Ĵ
   11      GND   GROUND          36      BSY    BUSY          
Ĵ
   12      DB5   DATA BIT 5      37      GND    GROUND        
Ĵ
   13      GND   GROUND          38      ACK    ACKNOWLEDGE   
Ĵ
   14      DB6   DATA BIT 6      39      GND    GROUND        
Ĵ
   15      GND   GROUND          40      RST    RESET         
Ĵ
   16      DB7   DATA BIT 7      41      GND    GROUND        
Ĵ
   17      GND   GROUND          42      MSG    MEGSSAGE      
Ĵ
   18      DBP   DATA PARITY     43      GND    GROUND        
Ĵ
   19      GND   GROUND          44      SEL    SELECT        
Ĵ
   20      GND   GROUND          45      GND    GROUND        
Ĵ
   21      GND   GROUND          46      C/D    CONTROL/DATA  
Ĵ
   22      GND   GROUND          47      GND    GROUND        
Ĵ
   23      GND   GROUND          48      REQ    REQUEST       
Ĵ
   24      GND   GROUND          49      GND    GROUND        
Ĵ
   25      GND   GROUND          50      I/O    INPUT/OUTPUT  




ACK (Acknowledge): A signal driven by an Initiator to indicate an
acknowledgement for a REQ/ACK data transfer handshake.

ATN (Attention): A signal driven by an Initiator to indicate the
attention condition.

BSY (Busy): An "or-tied" signal which indicates that the bus is in
use.

C/D (Control/Data): A signal driven by a Target. It indicates whether
control or data information is on the data bus. True indicates
Control.

DB(7-0) (Data Bus): Contains the data that is sent from one device to
the other. Driven by either device, as determined by the state of the
I/O signal.

DB(P) (Data Bus Parity): Contains the parity bit for the data that is
sent on DB(7-0) from one device to the other during an information
transfer.

I/O (Input/Output): A signal driven by a Target which controls the
direction of data flow in the data bus, with respect to an Initiator.
True indicates input to the Initiator.

MSG (Message): A signal driven by a Target during the message phase.

REQ (Request): A signal driven by a Target to indicate a request for a
REQ/ACK data transfer handshake.

RST (Reset): An "or-tied" signal which indicates the reset condition.

SEL (Select): A signal used by an Initiator to select a Target or by a
Target to reselect an Intiator.


=====================================================================
SCSI - Differential


SCSI (Small Computer System Interface) is an intelligent device
interface that allows up to 8 devices (usually 7 plus the host system)
to be connected together. Unlike other older interfaces, requests on a
SCSI bus are just that, requests. For example, rather than the
low-level device commands like the familiar STEP+ and STEP- of ST412,
SCSI accesses data using the higher level SEEK to a location ( LBA or
logical block address on drives ).

Differential SCSI (Small Computer System Interface) varies from
standard SCSI at the bus level in that it is capable of operating up
to a 25 meter cable, and the electrical specifications are quite
different. Input voltages vary from a low of -7VDC to a high of
+12VDC. These high voltage changes are measured from the positive
( + or POS ) portion of a signal, in relation to the negative
( - or NEG ) signal of the same name.

These devices ARE NOT BUS COMPATIBLE with SCSI standard devices. they
are hovever command compatible. Attempting to share the SCSI bus with
a non-differential device will quite possibly damage the single-ended
SCSI device. The electrical specification follows the EIA RS-485-1983
standard. Pin designations are as follows :

Ŀ
PIN NUMBERSIGNAL DESCRIPTION    PIN NUMBERSIGNAL   DESCRIPTION    
Ĵ
    1      GND   SHIELD GROUND      26    TERMPWR TERMINATION PWR 
Ĵ
    2      GND   GROUND             27      GND    GROUND         
Ĵ
    3     +DB0   POS DATA BIT 0     28      GND    GROUND         
Ĵ
    4     -DB0   NEG DATA BIT 0     29     +ATN    POS ATTENTION  
Ĵ
    5     +DB1   POS DATA BIT 1     30     -ATN    NEG ATTENTION  
Ĵ
    6     -DB1   NEG DATA BIT 1     31      GND    GROUND         
Ĵ
    7     +DB2   POS DATA BIT 2     32      GND    GROUND         
Ĵ
    8     -DB2   NEG DATA BIT 2     33     +BSY    POS BUSY       
Ĵ
    9     +DB3   POS DATA BIT 3     34     -BSY    NEG BUSY       
Ĵ
   10     -DB3   NEG DATA BIT 3     35     +ACK   POS ACKNOWLEDGE 
Ĵ
   11     +DB4   POS DATA BIT 4     36     -ACK   NEG ACKNOWLEDGE 
Ĵ
   12     -DB4   NEG DATA BIT 4     37     +RST    POS RESET      
Ĵ
   13     +DB5   POS DATA BIT 5     38     -RST    NEG RESET      
Ĵ
   14     -DB5   NEG DATA BIT 5     39     +MSG    POS MESSAGE    
Ĵ
   15     +DB6   POS DATA BIT 6     40     -MSG    NEG MESSAGE    
Ĵ
   16     -DB6   NEG DATA BIT 6     41     +SEL    POS SELECT     
Ĵ
   17     +DB7   POS DATA BIT 7     42     -SEL    NEG SELECT     
Ĵ
   18     -DB7   NEG DATA BIT 7     43     +C/D   POS COMMAND/DATA
Ĵ
   19     +DBP   POS PARITY BIT     44     -C/D   NEG COMMAND/DATA
Ĵ
   20     -DBP   NEG PARITY BIT     45     +REQ    POS REQUEST    
Ĵ
   21     DIFFSENNOT USED           46     -REQ    NEG REQUEST    
Ĵ
   22      GND   GROUND             47     +I/O   POS INPUT/OUTPUT
Ĵ
   23      GND   GROUND             48     -I/O   NEG INPUT/OUTPUT
Ĵ
   24      GND   GROUND             49      GND    GROUND         
Ĵ
   25     TERMPWRGROUND             50      GND    GROUND         






=================================================================
AT Interface
40-pin Cable
-----------------------------------------------------------------

AT INTERFACE SIGNAL PIN ASSIGNMENTS


     PIN       NAME                     DESCRIPTION
_________________________________________________________________________

     01       /Host        (From Host, Active Low) Reset signal from
              Reset        the host.

     02      Ground                     - - - -

   03-18     - - -         Host data 0-15 to/from host. 16-bit tris-
                           tate, bidirectional data bus between host
                           and drive.  The lower 8-bits of host data
                           (0-7) are used for register and ECC access.
                           All 16-bits are used for data transfers.

     19      Ground                    - - - -

     20       Key          An unused pin, which is clipped off at the
                           drive to prevent incorrect cable attach-
                           ment.

     21     Reserved                   - - - -

     22      Ground                    - - - -

     23      /HIOW         (From Host, Active Low) Host I/O write
                           strobe. Edge clocks data from the host data
                           bus to I/O register.

    24       Ground                    - - - -

    25       /HIOR         (From Host, Active Low) Host I/O read
                           strobe. Trailing edge clocks data from host
                           data bus to I/O register.

    26       Ground                    - - - -

    27      Reserved                   - - - -

    28      Host ALE       (From Host,Active High) Host address latch
                           enable. Used to qualify host address lines.
                           Host addresses are latched on the trailing
   this has been changed                        edge of Host ALE. The drive does not use
                           this signal.

    29      Reserved                   - - - -

    30       Ground                    - - - -

    31       IRQ14         (To Host, Tristate, Active High) Interrupt
                           request from drive to host.  The host may
                           enable/disable the interrupt by clearing/
                           setting the /IEN bit of the Digital Output
                           register of the task file.  The signal is
                           in a high impedance state when the drive is
                           not selected or when the /IEN bit of the
                           Digital Output register is set.  The signal
                           is cleared when host performs a status read
                           from drive.

    32       /HOST         (To Host, Tristate, Active Low) When active
             I/016         it indicates to host that the 16-bit Data
                           register is addressed and the drive is
                           ready to send/receive a 16-bit word.

    33        Host         (From Host, Active High) Host I/O address
             ADDR1         line 1.

    34      /PDIAG         (Active Low) Passed diagnostics.  Used by
                           Slave to signal to Master drive that Slave
                           has passed its internal diagnostics.  See
                           note 3.

    35       Host          (From Host, Active Low) Host I/O address
            ADDR0          line 0.

    36       Host          (From Host, Active High) Host I/O address
            ADDR2          line 2.

    37      /HOST          (From Host, Active Low) Host I/O chip
             CSO           select decoded from host address lines.
                           When active, one of the registers in the
                           range 01F0HEX through 01F7HEX is selected.

    38      /HOST          (From Host, Active Low) Host I/O chip
             CSI           select decoded from host address lines.
                           When active, one of the registers in the
                           range 03F0HEX through 0347HEX is selected.

    39      /HOST          (To Host, Active Low) Dual purpose pin.
           SLV/ACT         When drive is Slave (SLV), this pin is used
                           during a Diagnostic command to signal to
                           the Master that a Slave is present.  Drive
                           Activity to host: It is active when the
                           drive is executing a command.  May be used
                           by host drive an activity LED.

    40      Ground                     - - - -


    Notes:

    1. Signal beginning with (/) is active low.

    2. Reserved and Ground pins do not have directions.

    3. /PDIAG and Host/SLV are used for communication between
       Master and Slave.




=============================
XT Interface
(40-pin cable)
-----------------------------

              1.0 XT HOST/DRIVE INTERFACE PIN ASSIGNMENTS


   PIN        SIGNAL      DESCRIPTION
__________________________________________________________________


    1           RES       (From Host,Active High) Bus Reset signal

 3,5,7,9     DATA BUS     Host data to/from host.8-bit tristate,bi-
  11,13                   directional data bus between host and drive.
  15,17                   Used for transferring Status, Data and
                          Control information.

   19           GND       Ground

   20           Key       An unused pin, which is clipped off at the
                          drive to prevent incorrect cable attachment.

   21           AEN       (From Host, Active High) Host address
                          enable, which is asserted during a DMA
                          cycle to disable the decoding of I/O port
                          addresses.

   23          /IOW       (From Host, Active Low) Host I/O write
                          signal for writing data to an I/O port
                          address.

   25          /IOR       (From Host, Active Low) Host I/O read
                          signal for reading data from an I/O port
                          address.

   27          /DACK      (From Host, Active Low) DMA acknowledge
                          signal asserted in response to the DMA
                          Request signal. This signal enables DMA
                          data transfer when either /IOR or /IOW
                          signals are active.

   29           DRQ       (To Host, Active High) DMA Request as-
                          serted by the drive to initiate a DMA
                          transfer.

   31           IRQ       (To Host, Active High) Interupt Request
                          asserted by the drive to cause an interrupt
                          to the host.

 33,35        SA1,SA0     (From Host, Active High) Host I/O address
                          lines 0 and 1 for selecting the drive's
                          I/O ports.

   37           /CS       (From Host, Active Low) Card Select signal
                          asserted by the host to address the drive's
                          I/O ports.

   39        /ACTIVE      (To Host, Active Low) Drive Activity signal
                          asserted by the drive when it is processing
                          a command.  Can be used to drive an external
                          LED indicator.

NOTE:  All other even-numbered pins are ground.


