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     1                                                              22 
   1. D0 Data bus line 0                  A. D1 Data bus line 1 
   2. D2 Data bus line 2                  B. D4 Data bus line 4 
   3. D3 Data bus line 3                  C. D5 Data bus line 5 
   4. D7 Data bus line 7                  D. D6 Data bus line 6 
   5. A0 Address bus line 0               E. A2 Address bus line 2 
   6. A7 Address bus line 7               F. A9 Address bus line 9 
   7. A1 Address bus line 1               H. A13 Address bus line 13 
   8. A8 Address bus line 8               J. A4 Address bus line 4 
   9. A5 Address bus line 5               K. A11 Address bus line 11 
 10. A3 Address bus line 3               L. A12 Address bus line 12 
 11. A10 Address bus line 10             M. /S5 Select $A000-$BFFF 
 12. A6 Address bus line 6               N. Select line output to Slot 1 pin 
 M 
 13. R/W Late 2,3                        P. /S4 Select $8000-$9FFF 
 14. Phi2 Phase 2 clock                  R. Select line output to Slot 1 pin 
 P 
 15. RASTIME Row Address Strobe Tie      S. /S3 Select $6000-$7FFF 
 16. R/W Early                           T. Select line output to Slot 1 pin 
 S 
 17. /REF RAM Refresh                    U. /S2 Select $4000-$5FFF 
 18. Select line input from Slot 1 pin T V. NC Not Connected 
 19. Vcc +5V                             W. Vcc +5V 
 20. Vbb -5V                             X. Vbb -5V 
 21. Vdd +12V                            Y. Vdd +12V 
 22. Vss GND Ground                      Z. Vss GND Ground 
  
 RAM Module Slot 3 (rear RAM slot; 800 only): 
     A  B  C  D  E  F  H  J  K  L  M  N  P  R  S  T  U  V  W  X  Y  Z    Edge 
     -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  - 
 Connector 
     -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  - 
 22/44 
     1                                                              22 
   1. D0 Data bus line 0                  A. D1 Data bus line 1 
   2. D2 Data bus line 2                  B. D4 Data bus line 4 
   3. D3 Data bus line 3                  C. D5 Data bus line 5 
   4. D7 Data bus line 7                  D. D6 Data bus line 6 
   5. A0 Address bus line 0               E. A2 Address bus line 2 
   6. A7 Address bus line 7               F. A9 Address bus line 9 
   7. A1 Address bus line 1               H. A13 Address bus line 13 
   8. A8 Address bus line 8               J. A4 Address bus line 4 
   9. A5 Address bus line 5               K. A11 Address bus line 11 
 10. A3 Address bus line 3               L. A12 Address bus line 12 
 11. A10 Address bus line 10             M. /EXSEL External Select 
 12. A6 Address bus line 6               N. Not connected 
 13. R/W Late 2,3                        P. D6XX /CS Chip Select $D6xx 
 14. Phi2 Phase 2 clock                  R. Not connected 
 15. RASTIME Row Address Strobe Time     S. Not connected 
 16. R/W Early                           T. Not connected 
 17. /REF RAM Refresh                    U. Select line in from Slot 1 pin N 
 18. Select line input from Slot 1 pin R V. D5XX /CS Chip Select $D5xx 
 19. Vcc +5V                             W. Vcc +5V 
 20. Vbb -5V                             X. Vbb -5V 
 21. Vdd +12V                            Y. Vdd +12V 
 22. Vss GND Ground                      Z. Vss GND Ground 
  
 Parallel Bus Interface (PBI) (600XL and 800XL only): 
   1                                                                       49 
   -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  - 
   -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  - 
   2                                                                       50 
                    Edge Connector 25/50 
    1. GND Ground                        2. /EXTSEL External Select (Input) 
    3. A0 Address Line 0 (Output)        4. A1 Address Line 1 (Output) 
    5. A2 Address Line 2 (Output)        6. A3 Address Line 3 (Output) 
    7. A4 Address Line 4 (Output)        8. A5 Address Line 5 (Output) 
    9. A6 Address Line 6 (Output)       10. GND Ground 
   11. A7 Address Line 7 (Output)       12. A8 Address Line 8 (Output) 
   13. A9 Address Line 9 (Output)       14. A10 Address Line 10 (Output) 
   15. A11 Address Line 11 (Output)     16. A12 Address Line 12 (Output) 
   17. A13 Address Line 13 (Output)     18. A14 Address Line 14 (Output) 
   19. GND Ground                       20. A15 Address Line 15 (Output) 
   21. D0 Data Line 0 (In/Out)          22. D1 Data Line 1 (In/Out) 
   23. D2 Data Line 2 (In/Out)          24. D3 Data Line 3 (In/Out) 
   25. D4 Data Line 4 (In/Out)          26. D5 Data Line 5 (In/Out) 
   27. D6 Data Line 6 (In/Out)          28. D7 Data Line 7 (In/Out) 
   29. GND Ground                       30. GND Ground 
   31. BPhi2 Buffered Phase 2 Clock(Out)32. GND Ground 
   33. Reserved                         34. /RST Reset (Output) 
   35. /IRQ Interrupt Request (Input)   36. RDY Ready (Input) 
   37. Reserved                         38. EXTENB External Decoder Enable 
 (Out) 
   39. Reserved                         40. /REF Refresh (Output) 
   41. /CAS Column Address Strobe (Out) 42. GND Ground 
   43. /MPD Math Pack Disable (Input)   44. /RAS Row Address Strobe (Output) 
   45. GND Ground                       46. LR/W Latched Read/Write (Output) 
   47. 600XL: +5V                       48. 600XL: +5V 
       800XL: Reserved                      800XL: Reserved 
   49. AUDIO Audio In (Input)           50. GND Ground 
  
 Enhanced Cartridge Interface (ECI)/Expansion port (130XE, 800XE, & many 
 65XE) 
       A  B  C  D  E  F  H             Edge 
       -  -  -  -  -  -  -           Connector 
       -  -  -  -  -  -  -             7/14 
       1                 7 
 A. Reserved                       1. /EXTSEL External Select (Input) 
 B. /IRQ Interrupt Request (Input) 2. /RST Reset (Output) 
 C. /HALT (Input)                  3. D1XX /CS Chip Select $D1xx (In) 
 D. A13 Address Line 13 (Output)   4. /MPD Math Pack Disable (Input) 
 E. A14 Address Line 14 (Output)   5. AUDIO Audio In (Input) 
 F. A15 Address Line 15 (Output)   6. /REF Refresh (Output) 
 H. GND Ground                     7. +5V 
  
 Keyboard port (XE System console only): 
      8               1 
       o o o o o o o o     DA-15 Plug - male 
        o o o o o o o                 - pin numbering reverse of standard 
      15             9 
 1. /K2 Keyboard Scan (POKEY)       9. +5V 
 2. /K1 Keyboard Scan (POKEY)      10. +5V 
 3. /K0 Keyboard Scan (POKEY)      11. KBDETECT (GTIA/FGTIA) 
 4. /KR1 Keyboard Response (POKEY) 12. NC Not Connected 
 5. /K5 Keyboard Scan (POKEY)      13. GND Ground 
 6. /K4 Keyboard Scan (POKEY)      14. NC Not Connected 
 7. /K3 Keyboard Scan (POKEY)      15. GND Ground 
 8. /KR2 Keyboard Response (POKEY) 
  
 ------------------------------ 
  
 Subject: 1.16) Who designed the Atari 8-bit computers? 
  
 Many people were involved in the planning, design and engineering of the 8- 
 bit 
 Atari computers.  This section attempts to identify the key engineering 
 personnel at Atari and their roles, with the understanding that such a list 
 necessarily oversimplifies the true nature of complex product development. 
  
 Some sources: https://archive.org/details/JoeDecuirEngineeringNotebook1977, 
 https://archive.org/details/JoeDecuirEngineeringNotebook1978, 
 http://dougneubauer.com/atari/, 
 Goldberg/Vendel, Atari Inc.: Business is Fun, 2012, pp. 446-461, 694-700. 
  
 Atari 400/800: 
 Steven T. Mayer     - Chief system inventor; project proposal 
                        (Atari Cyan Engineering) 
 Jay G. Miner        - Project chief engineer; system co-inventor 
  
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 --- SoupGate-DOS v1.05 
  * Origin: you cannot sedate... all the things you hate (1:229/2)